职位描述
该职位还未进行加V认证,请仔细了解后再进行投递!
Job Description:
Intel labs is a world class research lab with the mission to drive research
and development of innovative technologies. In this position of ASIC backend
design lead, you will be in Intel labs China one of the top branches in Intel
labs, will be responsible for verification. You will also work very closely
with architect and designer to give them feedback for given design.
Qualifications:
Minimum qualifications are required to be initially considered for this
position. Preferred qualifications are in addition to the minimum requirements
and are considered a plus factor in identifying top candidates. Minimum
Qualifications: ? BE or equivalent degree? 5-8 years high performance
verification experience? Experience in high performance or lower power ASIC
design include CPU, DSP, or other ? Experience of a large-scale SOC design
verification? Fluent in RTL design using Verilog and experience with simulators
and waveform debugging tools. ? Hands on experience with System Verilog, UVM
and other verification technologies and tools.? Strong project management
skills and the ability to drive teamwork internally and externally? Good at
communication? Good spoken and written English.Preferred Qualifications: ?
Experience of CPU verification ? Experience of custom design ? Prior
verification experience in CPU system, PCIe, DDR, on-chip NOC, peripherals?
Successful tape-out experience of CPU, GPU, or any complex SoC highly
desirable? Master in CS or EE
Intel labs is a world class research lab with the mission to drive research
and development of innovative technologies. In this position of ASIC backend
design lead, you will be in Intel labs China one of the top branches in Intel
labs, will be responsible for verification. You will also work very closely
with architect and designer to give them feedback for given design.
Qualifications:
Minimum qualifications are required to be initially considered for this
position. Preferred qualifications are in addition to the minimum requirements
and are considered a plus factor in identifying top candidates. Minimum
Qualifications: ? BE or equivalent degree? 5-8 years high performance
verification experience? Experience in high performance or lower power ASIC
design include CPU, DSP, or other ? Experience of a large-scale SOC design
verification? Fluent in RTL design using Verilog and experience with simulators
and waveform debugging tools. ? Hands on experience with System Verilog, UVM
and other verification technologies and tools.? Strong project management
skills and the ability to drive teamwork internally and externally? Good at
communication? Good spoken and written English.Preferred Qualifications: ?
Experience of CPU verification ? Experience of custom design ? Prior
verification experience in CPU system, PCIe, DDR, on-chip NOC, peripherals?
Successful tape-out experience of CPU, GPU, or any complex SoC highly
desirable? Master in CS or EE
工作地点
地址:北京海淀区海淀区科学院南路2号融科资讯中心A座


职位发布者
Auro..HR
英特尔(中国)研究中心有限公司

-
IT服务·系统集成
-
200-499人
-
外商独资·外企办事处
-
海淀区科学院南路2号融科资讯中心A座8层
相似职位
-
数据开发工程师 20000-35000元海淀区 应届毕业生 本科北京小桔科技有限公司
-
后端软件开发工程师(abtest平台) 20000-35000元海淀区 应届毕业生 本科北京小桔科技有限公司
-
机器学习平台开发工程师 35000-50000元海淀区 应届毕业生 本科北京小桔科技有限公司
-
反入侵工程师 25000-45000元海淀区 应届毕业生 本科北京小桔科技有限公司
-
国际化金融信息安全bp 30000-50000元海淀区 应届毕业生 本科北京小桔科技有限公司
-
通用搜索组-pc搜索体验产品经理 30000-60000元海淀区 应届毕业生 本科百度在线网络技术(北京)有限公司